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dual 12-bit, high bandwidth, multiplying dac with 4-quadrant resistors and serial interface ad5415 rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features on-chip 4-qua d rant resistors allow flexible o u tput ranges 10 mhz multiplying bandwidt h 50 mhz serial i n terface 2.5 v to 5.5 v s u pply operation 10 v refer e nce input extended t e mperature r a nge: ?40 c to +1 25 c 24-lea d tssop package guarantee d m o notonic power-on reset daisy-chain m o de readback func tion 0.5 a t y pical c u rrent consumption applic ati o ns portable batter y -powered applications waveform gen e rators analog processing instrumentation applications programmable amplifiers and attenuators digitall y controlled calibratio n programmable filters and osci llators composite video ultrasound gain, offset, an d voltage trim ming general description the ad5415 1 is a cmos 12- b i t, d u a l -cha n n el, c u r r en t o u t p u t dig i t a l-to - a na lo g co n v er ter . thi s de vice op er a t es f r o m a 2.5 v to 5 . 5 v p o we r supply , ma k i ng it s u i t e d to b a tte r y - p owe r e d a p pl i - ca tion s as we l l as ma n y o t h e r a p p l ica t ion s . the a p plie d exter n al r e fer e n c e i n p u t v o l t a g e ( v ref ) det e r m in es th e f u l l -s cale o u t p u t c u r r en t. an in teg r a t e d f e e d bac k r e sis t o r (r fb ) p r o v ides tem p er a t ur e t r ackin g and f u l l -s c a le v o l t a g e o u t p u t w h en com b in e d wi t h a n ext e r n al c u r r en t-t o -v ol t a g e p r e c isio n a m pl i f ier . i n addi t i o n , t h is de vice con t a i n s a l l t h e 4-q u ad ra n t r e sis t o r s n e ces s a r y f o r b i p o la r o p er a t io n an d o t h e r co nf igur a t io n m o de s. t h i s d a c u t ilize s a d o u b le -b uf f e r e d 3-w i r e se rial i n t e rfa c e tha t is co m p a t i b le wi th s p i?, qs p i ?, mi cro w i r e?, a nd m o s t ds p in t e r f ace st andar d s. i n add i t i on, a s e r i a l d a t a o u t p i n (sd o ) al lo ws f o r da isy-c h a i nin g w h en m u l t i p le p a ckag es a r e us ed . d a t a r e adb a ck a l lo ws t h e us er t o r e ad t h e con t e n ts o f t h e d a c r e g i s t er v i a t h e s d o p i n. on p o w e r - u p , t h e in ter n al s h if t r e g i st er an d la t c h e s a r e f i l l e d w i t h zer o s, an d t h e d a c o u t p u t s a r e a t zer o s c a l e. a s a r e su l t o f m a n u fac t ur e o n a cmos sub m i- c r on pro c e s s , t h i s p a r t of f e r s exc e l l e n t 4 - qu a d r a n t m u lt ipl i c a t i on c h a r ac t e r i s t ics, wi t h la rg e - sig n a l m u l t i p l y in g ban d wid t h s o f 10 mh z. 1 us patent number 5,689,257. func tio n a l block di agram power-on reset input register dac register 12-bit r-2r dac b input register dac register 12-bit r-2r dac a shift register v dd sclk sdin gnd sdo sync ldac r3 2r r2 2r r1 2r r fb 2r r1 2r r fb 2r r3 2r r2 2r ad5415 r3a r2_3a r2a v ref a r1a r3b r2_3b r2b v ref b r1b r fb a i out 1a i out 2a i out 1b i out 2b r fb b clr 04461-0-001 fi g u r e 1 .
ad5415 rev. 0 | page 2 of 28 table of contents specifications ..................................................................................... 3 timing characteristics ................................................................ 5 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 te r m i no l o g y ...................................................................................... 9 typical performance characteristics ........................................... 10 general description ....................................................................... 15 dac section ................................................................................ 15 unipolar mode ............................................................................ 15 bipolar operation ....................................................................... 16 stability ........................................................................................ 16 single-supply applications ............................................................ 17 voltage switching mode of operation .................................... 17 positive output voltage ............................................................. 17 adding gain ................................................................................ 17 divider or programmable gain element ................................ 17 reference selection .................................................................... 18 amplifier selection .................................................................... 18 serial interface ................................................................................ 20 low power serial interface ....................................................... 20 control register ......................................................................... 20 sync function ........................................................................... 21 daisy-chain mode ..................................................................... 21 standalone mode ........................................................................ 21 ldac function .......................................................................... 21 microprocessor interfacing ....................................................... 22 pcb layout and power supply decoupling ................................ 24 evaluation board for the dac ................................................. 24 power supplies for the evaluation board ................................ 24 outline dimensions ....................................................................... 28 ordering guide .......................................................................... 28 revision history 7/04revision 0: initial version
ad5415 rev. 0 | page 3 of 28 specifications temperature range for y version: ?40c to +125c. v dd = 2.5 v to 5.5 v, v ref = 10 v, i out 2a, i out 2b = 0 v; all specifications t min to t max , unless otherwise noted. dc performance measured with op1177, ac performance with ad8038, unless otherwise noted. table 1. parameter min typ max unit conditions static performance resolution 12 bits relative accuracy 1 lsb differential nonlinearity ?1/+2 lsb guaranteed monotonic gain error 25 mv gain error temperature coefficient 1 5 ppm fsr/c bipolar zero code error 25 mv output leakage current 1 na data = 0x0000, t a = 25c, i out 1 10 na data = 0x0000, i out 1 reference input 1 typical resistor tc = ?50 ppm/c reference input range 10 v v ref a, v ref b input resistance 8 10 12 k? dac input resistance v ref a to v ref b input resistance mismatch 1.6 2.5 % typ = 25c, max = 125c r 1 , r fb resistance 16 20 24 k? r 2 , r 3 resistance 16 20 24 k? r 2 to r 3 resistance mismatch 0.06 0.18 % typ = 25c, max = 125c digital inputs/output 1 input high voltage, v ih 1.7 v v dd = 2.5 v to 5.5 v input low voltage, v il 0.8 v v dd = 2.7 v to 5.5 v 0.7 v v dd = 2.5 v to 2.7 v input leakage current, i il 1 a input capacitance 10 pf v dd = 4.5 v to 5.5 v output low voltage, v ol 0.4 v i sink = 200 a output high voltage, v oh v dd ? 1 v i source = 200 a v dd = 2.5 v to 3.6 v output low voltage, v ol 0.4 v i sink = 200 a output high voltage, v oh v dd ? 0.5 v i source = 200 a dynamic performance 1 reference multiplying bandwidth 10 mhz v ref = 5 v p-p, dac loaded all 1s output voltage settling time 90 160 ns measured to 4 mv of fs; r load = 100 ?, c load = 0s, 15 pf, dac latch alternately loaded with 0s and 1s digital delay 20 40 ns digital-to-analog glitch impulse 3 nv -s 1 lsb change around major carry, v ref = 0 v multiplying feedthrough error ?75 db dac latch loaded with all 0s, reference = 10 khz output capacitance 2 pf dac latches loaded with all 0s 4 pf dac latches loaded with all 1s digital feedthrough 5 nv-s feedthrough to dac output with cs high and alternate loading of all 0s and all 1s total harmonic distortion ?75 db v ref = 5 v p-p, all 1s loaded, f = 1 khz ?75 db v ref = 5 v, sine wave generated from digital code output noise spectral density 25 nv/hz @ 1 khz
ad5415 rev. 0 | page 4 of 28 parameter min typ max unit conditions sfdr performance (wideband) clock = 10 mhz 500 khz f out 55 db 100 khz f out 63 db 50 khz f out 65 db clock = 25 mhz 500 khz f out 50 db 100 khz f out 60 db 50 khz f out 62 db sfdr performance (narrow-band) clock = 10 mhz 500 khz f out 73 db 100 khz f out 80 db 50k hz f out 87 db clock = 25 mhz 500 khz f out 70 db 100 khz f out 75 db 50k hz f out 80 db intermodulation distortion clock = 10 mhz f 1 = 400 khz, f 2 = 500 khz 65 db f 1 = 40 khz, f 2 = 50 khz 72 db clock = 25 mhz f 1 = 400 khz, f 2 = 500 khz 51 db f 1 = 40 khz, f 2 = 50 khz 65 db power requirements power supply range 2.5 5.5 v i dd 10 a logic inputs = 0 v or v dd power supply sensitivity 1 0.001 %/% ?v dd = 5% 1 guaranteed by design and characterization, not subject to production test.
ad5415 rev. 0 | page 5 of 2 8 timing characteristics t e m p er a t ur e ran g e f o r y v e rsio n: ?40c t o +125c. s e e f i gur e 2 a nd f i gur e 3. g u ar a n te e d b y de s i g n a nd ch ar a c te r i z a t i on, not subj e c t to pro d u c t i on te st . al l in p u t sig n als a r e s p ecif ie d wi t h tr = tf = 1 n s (10% t o 90% o f v dd ) and t i me d f r om a vol t age l e vel of ( v il + v ih )/2. v dd = 2.5 v t o 5.5 v , v ref = 5 v , i ou t 2 = 0 v . a l l sp e c if ic a t io n s t mi n to t max , u n l e ss ot he r w i s e not e d. table 2. parameter limit at t min , t ma x unit conditions/comments 1 f sclk 50 mhz max maximum cloc k frequency t 1 20 ns min sclk cycle time t 2 8 ns min sclk high time t 3 8 ns min sclk low time t 4 13 ns min sync falling edge to sclk falling edge setup time t 5 5 ns min data setup time t 6 4 ns min data hold time t 7 5 ns min sync rising edge to sclk falling edge t 8 30 ns min minimum sync high time t 9 0 ns min sclk falling edge to ldac falling edge t 10 12 ns min ldac pulse wid t h t 11 10 ns min sclk falling edge to ldac rising edge t 12 2 25 ns min sclk active edge to sdo valid, strong sdo driver 60 ns min sclk active edge to sdo valid, weak sdo driver 1 fa lli n g or ri si n g e d ge a s d e t e rm i n ed b y t h e con t r ol bi t s of se ri a l wo rd. st ron g or wea k sd o dri v e r s e lect e d vi a t h e c o n t r ol r e gister. 2 dais y-chain and read back modes cannot oper ate at maximum cl ock frequen c y. sdo timing s p ecif ications meas ured with a load circu it , as s h o w n i n . f i g u r e 4 t 1 t 2 t 3 t 7 t 8 t 4 t 5 t 6 t 9 t 10 t 11 db15 db0 sclk din ldac 1 ldac 2 sync notes 1 asynchronous ldac update mode 2 synchronous ldac update mode alternatively, data can be clocked into input shift register on rising edge of sclk as determined by control bits. timing as above, with sclk inverted. 04461-0-002 fi g u r e 2 . s t a n d a l o n e m o d e ti ming d i ag r a m
ad5415 rev. 0 | page 6 of 2 8 04461-0-003 t 8 t 7 t 12 t 1 t 3 t 2 t 4 t 5 t 6 db15 (n) db15 (n+1) db0 (n) db0 (n+1) db15 (n) db0 (n) sclk sync sdin sdo alternatively, data can be clocked into input shift register on rising edge of sclk as determined by control bits. in this case, data would be clocked out of sdo on falling edge of sclk. timing as above, with sclk inverted. f i g u re 3. d a is y- chain and r e adb a ck m o des ti ming d i a g r a m 200 ai ol 200 ai oh to output pin c l 50pf v oh (min) + v ol (max) 2 04461-0-004 f i gure 4. l o ad cir c uit for sdo t i ming sp ec ific ations
ad5415 rev. 0 | page 7 of 2 8 absolute maximum ratings t r a n sien t c u r r en ts o f u p t o 100 ma do n o t ca us e scr l a t c h-u p . t a = 2 5 c , u n l e ss ot he r w i s e not e d. table 3. p a r a m e t e r r a t i n g v dd to gnd ?0.3 v to +7 v v ref , r fb to gnd ?12 v to +12 v i ou t 1, i ou t 2 to gn d ?0.3 v to +7 v input current to any pin ex cept supplies 10 ma logic inputs and output 1 ?0.3 v to v dd + 0.3 v operating tem p erature range extended (y ver s ion) ?40c to +125c storage temperature range ?65c to +150c junction tempe r ature 150c 24-lead tssop ja thermal impedance 128c/w lead temperature, soldering ( 10 second s) 300c ir reflow, peak temperature ( < 20 second s) 235c 1 overvo l tages at sclk, sync , and din are cl a m ped by internal d i od es . current should be limited to the maximum ratings given. s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y a nd f u n c t i o n al op era t io n o f t h e de v i ce a t t h es e o r a n y o t h e r con d i t io n s ab o v e t h o s e i n dica t e d in t h e op era t io nal s e c t io n o f t h is sp e c if ic a t io n is no t im plie d . e x p o sur e t o a b s o l u te max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . esd caution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad5415 rev. 0 | page 8 of 2 8 pin conf iguration and fu nction descriptions 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 ad5415 top view (not to scale) sdin sclk gnd v ref a i out 1a i out 2a r fb a r1a r3a r2_3a r2a clr v dd v ref b i out 1b i out 2b r fb b r1b r3b r2_3b r2b ldac sdo sync 04461-0-005 f i gure 5. pin config ur ation ta ble 4. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic function 1 i ou t 1a dac a current output. 2 i ou t 2a dac a analog ground. t h is pin should norma lly be tied to the a n alog ground of the system, but can be bi ased to achieve single- s upply operatio n . 3 r fb a dac feedback resistor pin. t h is pin esta blis hes volt age output for the dac by c o nnecting to the ex ternal amplifier output. 4 C 7 r 1 a C r 3 a dac a 4-quad ra nt resistors. t h e s e pins all o w a n u mber of config uration modes, i n cluding bipo la r operation, with minimum exter n al com pone n ts. 8 v ref a dac a referenc e voltage input pin. 9 gnd ground pin. 10 ldac load dac input. this pin allows asynchro nous o r synchron ous upda tes to the dac output. the dac is asynchronously updated when this sign al goes low. alternativel y, if this line is h e ld permanent l y low, an automatic or synchron ous upd a te mod e is sele cted wher eby the dac is update d on the 16th clock fal l ing edge when the devic e is in standalon e mode or on the rising edge of sync when in daisy-c h ain mode. 11 sclk serial clock input. by default, d a ta is clocked into the input shift register on the falling edge of the serial clock input. alternatively, by means of the serial control bits, th e devic e can be co nfigured such that data is cloc ked in to the shift register on the rising edge of sclk. 12 sdin serial data inpu t. data is clocked in to the 16-bit input register on the acti ve edge of the serial clock input. by default, on pow er-up, data is clo c ked in to the sh ift register on the falling ed ge of sclk. t h e control bits a llo w the user to change the active edge to the rising edge. 13 sdo serial data output. this pin allows a number of parts to be daisy-chained. by defaul t, da ta is clocked into the shift register on the falling edge and out via sdo on the risi ng edge of sclk. data is always clocked out on the alternate edge to loading data to the shift register. writing the readback c o nt rol word to the shift register makes the dac register contents avai la ble for readba ck on the sdo pin, clocked out on the next 16 opp osite clo c k edges to the active clo c k edge. 14 sync active low control input. the frame synchron iz ation signa l for th e input data. when sync goes lo w , it powers on the sclk and di n buffers, and t h e input sh ift register is enabled. data is load ed to the shift register on the active ed ge of the following cl ock s . in stand a lon e mod e , the serial interface counts clocks, and data is latched to the shift register on the 16th active clock edge. 15 clr active low control input. this pin clea rs the dac output, input, and dac registers. configuratio n mod e allo ws t h e user to enable t h e hardware clr pin as a cle a r to ze ro scal e or mids c ale, a s required . 16 v dd positive power s u pply input. this part can be operated from a supply of 2.5 v to 5.5 v. 17 v ref b dac b reference voltage input pin. 1 8 C 2 1 r 1 b C r 3 b dac b 4-quad rant resistors. t h e s e pins all o w a n u mber of config uration modes, i n cluding bipo la r operation, with minimum of external compon e n ts. 22 r fb b dac b feedback resistor pin. t h is pin e s tabli s h e s vo ltage output for the dac by connecting to the ex ternal amplifier output. 23 i ou t 2b dac b analog ground. t h is pin should norma lly be tied to the a n alog ground of the system, but can be bi ased to achieve single- s upply operatio n . 24 i ou t 1b dac b current output.
ad5415 rev. 0 | page 9 of 2 8 terminology re l a ti ve a c c u r a c y rela t i v e acc u rac y o r en d p oin t n o nl inea r i ty is a m e as ur e o f th e maxim u m d e v i a t io n f r o m a st r a ig h t li ne p a ssing t h r o ug h t h e end p o i n t s o f t h e d a c t r a n sfer f u n c t i on. i t is me as ur e d a f t e r ad j u st ing fo r ze r o s c a l e a nd f u l l s c a l e, an d is n o r m a l ly ex p r ess e d in ls b o r as a p e r c en ta ge o f f u l l -s cale r e ading. d i f f erenti a l n o n l i n e a r i ty dif f er en t i al n o n l in e a r i ty is t h e dif f er en ce i n t h e m e as ur e d cha n ge and t h e ide a l 1 ls b chan ge b e twe e n an y tw o ad jace n t co des. a sp e c if i e d dif f er en t i a l no n l i n e a r i ty o f 1 ls b max i m u m o v er t h e o p era t i n g t e m p era t ur e ra n g e en s u r e s m o n o t o nici ty . ga in er r o r ga in er r o r o r f u l l -s cale er r o r is a me as ur e o f t h e o u t p ut er r o r b e tw e e n an ide a l d a c an d t h e ac t u al de vice ou t p u t . f o r t h es e d a cs, ide a l ma x i m u m o u t p ut i s v ref ? 1 ls b . ga in er r o r o f t h e d a cs is ad j u s t ab le t o zer o wi t h ext e r n al r e sis t a n ce. ou t p u t l e akage c u r r e n t o u t p u t le a k a g e c u r r en t is c u r r e n t t h a t f l o w s in t h e d a c ladder sw i t ch es w h en t h e y a r e t u r n e d o f f. f o r t h e i out 1 t e r m inal , i t can b e m e asur e d b y lo adin g a l l 0s to t h e d a c an d m e a s ur in g t h e i ou t 1 cu rr e n t . m i n i m u m cu rr e n t f l o w s i n th e i ou t 2 lin e w h en th e d a c is lo ade d wi t h al l 1s. ou t p u t c a pacita n c e ca pa c i t a n c e fr o m i ou t 1 o r i ou t 2 t o a g nd . o u tp u t c u r r e n t s e tt l i n g ti m e t h e a m o u n t o f ti m e i t ta k e s f o r th e o u t p u t t o set t le t o a speci- f i e d le v e l f o r a f u l l -s cale in p u t cha n g e . f o r th es e de vices, i t is s p ecif ie d wi t h a 100 ? r e sis t o r t o g r o u n d . di g i t a l-t o -ana l o g glit ch i m pu ls e the am o u n t o f c h a r g e in jec t e d f r o m th e dig i ta l in p u ts t o the a n alog o u t p u t w h en the in p u ts cha n g e s t a t e . this is n o r m al l y s p ecif ie d as t h e a r ea o f th e g l i t ch in ei t h er pa -s o r nv -s dep e n d - in g u p on w h et her t h e g l i t ch is m e as ur e d as a c u r r en t o r vol t age s i g n a l . dig i ta l f e e d thr o ug h w h en t h e de vic e is n o t s e le c t e d , hig h f r e q ue n c y log i c ac t i vi ty o n th e de v i ce s di gi tal i n p u t s i s ca p a ci ti v e l y co u p led th r o ugh t h e d e v i c e to show up a s noi s e on t h e i ou t p i ns and subs e q u e n t ly in t o t h e fol l o w i n g cir c ui t r y . this n o is e is dig i t a l fe e d t h r o ug h. m u l t iply in g f e e d thr o ug h e rro r the er r o r d u e to ca p a ci t i v e fe e d t h r o ug h f r o m t h e d a c re f e re nc e i n put to t h e d a c i ou t 1 t e rm i n al w h en all 0s a r e lo ade d t o the d a c. dig i ta l c r osstal k the g l i t ch i m p u ls e t r a n sfer r e d t o t h e o u t p u t s o f o n e d a c i n r e s p o n s e t o a f u l l -s cale co de c h a n g e (al l 0s t o al l 1s a nd vice v e rs a) in t h e i n p u t r e g i s t er o f t h e o t h e r d a c. i t is exp r es s e d in n v -s. ana l og c r ossta l k the g l i t ch i m p u ls e t r a n sfer r e d t o t h e o u t p u t o f o n e d a c d u e t o a ch ange i n t h e output of anot h e r d a c . i t i s me a s u r e d by lo adin g on e o f t h e i n p u t r e g i st e r s wi t h a f u l l -s c a le co de chan ge (al l 0s t o al l 1s a nd vice v e rs a), while k eep in g ld a c hig h . t h e n pu l s e ld a c lo w a n d m o ni t o r t h e o u t p u t o f t h e d a c w h os e dig i t a l co de was n o t chan ge d . t h e a r e a o f t h e g l i t ch is ex p r ess e d in n v -s. c h an nel-t o -c h a n n el i s ol a t i o n t h e prop or t i on of i n put s i g n a l f r om on e d a c r e f e re nc e i n put t h at ap p e a r s at t h e o u t p u t o f t h e o t h e r d a c a n d i s e x p r e s s e d in d b . ha r m o n i c d i s t or t i on the d a c is dr i v en b y a n ac r e fer e n c e . the ra t i o o f t h e r m s s u m o f th e h a rm o n i c s o f th e d a c o u t p u t t o th e fun d a m en tal v a l u e i s th e t o tal h a rm o n i c d i s t o r ti o n (t h d ). u s uall y o n l y th e lo w e r - o r der ha r m o n ic s a r e in cl ude d , such as s e cond to f i f t h. ( ) 1 2 5 2 4 2 3 2 2 log 20 v v v v v thd + + + = inte r m o d u l at i o n d i s t or t i on the d a c is dr i v en b y tw o com b i n e d si n e w a v e r e fer e n c es o f f r eq uen c ies fa and fb . dist o r tio n p r o d uc ts a r e p r o d uced a t s u m a nd dif f er e n ce f r e q uen c ies o f m f a nfb , w h er e m , n = 0, 1, 2, 3 . . . i n te r m o d u l a t i o n te r m s are t h o s e for w h i c h m or n is n o t e q ua l to zer o . t h e s e c o nd-o r der ter m s in cl ud e (fa + f b ) a nd (fa ? fb) a nd t h e thir d-o r der t e r m s a r e (2fa + fb), (2fa ? fb), (f + 2fa + 2fb) a nd (fa ? 2 f b). imd is def i n e d as ( ) l fundamenta the of amplitude rms products distortion diff and sum the of sum rms imd log 20 = c o m p li ance v o l t age r a n g e the maxi m u m ra n g e o f (o u t p u t) t e r m inal v o l t a g e fo r which t h e de vice p r o v i d es t h e sp e c if ie d ch a r ac t e r i st ics.
ad5415 rev. 0 | page 10 of 28 typical perf orm ance cha r acte ristics ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 0.8 1.0 inl ( l sb) 2000 1500 500 1 000 0 2500 3 000 3500 4000 code 04461-0-006 t a = 25c v ref = 10v v dd = 5v f i g u re 6. inl v s . co de (1 2-bit da c ) ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 0.8 1.0 dnl (ls b ) 2000 1500 500 1 000 0 2500 3 000 3500 4000 code 04461-0-007 t a = 25c v ref = 10v v dd = 5v f i g u re 7. dnl v s . code ( 12-b i t da c ) ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 inl ( l sb) 6 5 34 27 8 reference voltage 04461-0-008 9 1 0 max inl min inl t a = 25c v ref = 10v v dd = 5v f i gure 8. inl v s . r e f e r e nc e v o lt age ?0.70 ?0.65 ?0.60 ?0.55 ?0.50 ?0.45 ?0.40 dnl (ls b ) 6 5 34 27 8 reference voltage 04461-0-009 9 1 0 min dnl t a = 25 c v ref = 10v v dd = 5v f i gure 9. dnl v s . r e fer e n c e v o ltag e ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 e rror (mv ) ? 6 0 ? 40 ?20 0 20 40 60 80 100 120 140 temperature ( c) 04461-0-010 v dd = 5v v dd = 2.5v v ref = 10v f i gure 10. g a in e r ror v s . t e mper atur e input voltage (v) curre nt (ma) 8 5 0 5.0 7 6 3 1 4 2 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 t a = 25 c v dd = 5v v dd = 3v v dd = 2.5v 04461-0-011 f i gure 11. sup p l y current v s . l o gic i n p u t v o ltag e
ad5415 rev. 0 | page 11 of 28 0 0.2 0.4 0.6 0.8 1.0 i out le akage (na) 1.2 1.4 1.6 40 20 ?2 0 0 ? 4 0 6 0 8 0 100 1 2 0 temperature (c) 04461-0-012 i out 1 v dd 5v i out 1 v dd 3v f i g u re 12. i ou t 1 l e akag e cu rrent v s . t e mpe r at u r e 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 curre nt ( a) ? 6 0 ? 40 ? 2 0 0 20 40 60 80 100 120 140 temperature ( c) 04461-0-013 t a = 25c v dd = 5v v dd = 2.5v all 0s all 1s all 0s all 1s f i gure 13. sup p l y current v s . t e mper at ur e 0 2 4 6 8 10 12 14 i dd (ma) 10k 1k 10 100 1 100k 1m 10 m 100m frequency (hz) 04461-0-014 t a = 25c loading zs to fs v dd = 5v v dd = 3v v dd = 2.5v f i gure 14. sup p l y current v s . u p date r a te ? 102 ?66 ?54 ?42 ?30 ?18 ?6 6 1 100 1k 10k 100k 1m 10m 100m frequency (hz) g a in ( d b ) t a = 25 c loading zs to fs 0 ?60 ?48 ?36 ?24 ?12 ?84 ?72 ?78 ?90 ?96 t a = 25 c v dd = 5v v ref = 3.5v input c comp = 1. 8p f ad8038 amplifier all on db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 all off 04461-0-015 10 f i gure 15. reference mult iplying b a nd width vs. f r equenc y and code ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 gain ( d b) 10k 1k 10 1 0 0 1 100k 1m 10m 100 m frequency (hz) 04461-0-016 t a = 25c v dd = 5v v ref = 3.5v c comp = 1.8pf ad8038 amplifier f i g u re 16. r e f e rence m u lt iply i n g b a nd widt hCa ll o n es l o aded ?9 ?6 ?3 0 3 10k 100k 1m 10m 100m frequency (hz) t a = 25c v dd = 5v ga in ( d b ) 04461-0-017 v ref = 2v, ad8038 c c 1.47pf v ref = 2v, ad8038 c c 1pf v ref = 0.15v, ad8038 c c 1pf v ref = 0.15v, ad8038 c c 1.47pf v ref = 3.51v, ad8038 c c 1.8pf f i gure 17. reference mult iplying b a nd width vs. f r equenc y and comp en s a t i on cap a c i to r
ad5415 rev. 0 | page 12 of 28 ?0.010 ?0.005 0.005 0.025 0.035 0.045 0.015 0 0.020 0.030 0.040 0.010 output voltage (v) 0 2 0 4 0 6 0 8 0 100 120 140 160 180 200 time (ns) 04461-0-018 t a = 25c v ref = 0v ad8038 amplifier c comp = 1.8pf 7ff to 800h 800 to 7ffh v dd = 5v v dd = 3v v dd = 3v v dd = 5v f i g u re 18. m i ds c a l e t r ans i t i on, v ref = 0 v output voltage (v) 0 2 0 4 0 6 0 8 0 100 120 140 160 180 200 time (ns) 04461-0-019 ? 1.77 ? 1.76 ? 1.75 ? 1.74 ? 1.73 ? 1.72 ? 1.71 ? 1.70 ? 1.69 ? 1.68 7ff to 800h 800 to 7ffh v dd = 5v v dd = 3v v dd = 3v v dd = 5v t a = 25c v ref = 3.5v ad8038 amplifier c comp = 1.8pf f i g u re 19. m i ds c a l e t r ans i t i on, v ref = 3 . 5 v ?120 ?100 ?80 ?60 0 20 1 100 1k 10k 100k 1m 10m frequency (hz) ?40 ?20 t a = 25 c v dd = 3v amp = ad8038 full scale zero scale psrr (d b) 04461-0-020 10 f i gure 20. p o wer s u p p ly rej e c t ion vs. f r equ e nc y ?9 0 ?8 5 ?8 0 ?7 5 ?7 0 ?6 5 ? 60 thd + n (db) 100 1k 1 1 0 10k 100k 1m frequency (hz) 04461-0-021 t a = 25 c v dd = 3v v ref = 3.5v p-p f i gure 21. thd and noise vs. f r equenc y 0 20 40 60 80 100 s f dr (db) 0 2 0 4 0 6 0 8 0 100 120 140 160 180 200 f out (khz) 04461-0-022 t a = 25c v ref = 3.5v ad8038 amplifier mclk = 1mhz mclk = 200khz mclk = 0.5mhz f i g u re 22. wideb a n d sfdr v s . f ou t fre q u e n c y 0 10 20 30 40 50 60 70 80 90 s f dr (db) 0 100 200 300 400 500 600 700 800 900 1000 f out (khz) 04461-0-023 mclk = 5mhz mclk = 10mhz mclk = 25mhz t a = 25c v ref = 3.5v ad8038 amplifier f i g u re 23. wideb a n d sfdr v s . f ou t fre q u e n c y
ad5415 rev. 0 | page 13 of 28 04461-0-024 ?9 0 ?7 0 ?5 0 ?3 0 ?1 0 s f dr ( d b) 0 frequency (mhz) ?8 0 ?6 0 ?4 0 ?2 0 0 t a = 25 c v dd = 5v amp = ad8038 65k codes 24 68 1 0 1 2 f i g u re 24. wideb a n d sfdr , f ou t = 1 00 k h z, c l o c k = 2 5 m h z 04461-0-025 ?100 ?7 0 ?5 0 ?3 0 ?1 0 s f dr ( d b) 0 frequency (mhz) ?8 0 ?6 0 ?4 0 ?2 0 0 t a = 25 c v dd = 5v amp = ad8038 65k codes 0.5 1.5 3.0 3.5 4.0 1.0 2.0 2.5 4.5 5.0 ?9 0 f i g u re 25. wideb a n d sfdr , f ou t = 5 00 k h z, c l o c k = 1 0 m h z 04461-0-026 ?9 0 ?7 0 ?5 0 ?3 0 ?1 0 s f dr ( d b) 0 frequency (mhz) ?8 0 ?6 0 ?4 0 ?2 0 0 0.5 1.5 3.0 3.5 4.0 1.0 2.0 2.5 4.5 5.0 t a = 25 c v dd = 5v amp = ad8038 65k codes f i g u re 26. wideb a n d sfdr , f ou t = 5 0 k h z, c l o c k = 1 0 m h z 04461-0-027 frequency (mhz) t a = 25 c v dd = 3v amp = ad8038 65k codes ? 100 ?70 ?50 ?30 ?10 s f dr ( d b) 250 750 300 350 400 650 700 ?80 ?60 ?40 ?20 0 ?90 450 500 550 600 f i gure 27. na rro w - band spec tr al r e s p ons e , f ou t = 5 00 k h z, cl ock = 25 m h z 04461-0-028 ?120 ?6 0 ?2 0 sf d r (d b ) 50 150 frequency (mhz) 60 70 80 130 140 ?8 0 ?4 0 0 20 ?100 90 100 110 120 t a = 25 c v dd = 3v amp = ad8038 65k codes f i gure 28. na rro w - band sf dr , f ou t = 1 00 k h z, mcl k = 25 mh z 04461-0-029 frequency (mhz) ? 100 ?70 ?50 ?30 ?10 (d b ) 70 120 75 80 85 115 ?80 ?60 ?40 ?20 0 ?90 90 100 105 110 t a = 25 c v dd = 3v amp = ad8038 65k codes 95 f i gure 29. na rro w - band imd , f ou t = 90 kh z, 10 0 k h z, c l oc k = 1 0 m h z
ad5415 rev. 0 | page 14 of 28 04461-0-030 ?100 ?40 ?20 (db) ?50 ?30 ?10 ?90 ?60 ?70 ?80 0 400 frequency (khz) 50 300 350 100 150 200 250 0 t a = 25 c v dd = 5v amp = ad8038 65k codes f i g u re 30. wideb a n d im d , f ou t = 90 kh z, 1 0 0 kh z , cl ock = 25 m h z 100 1k 10k 100k frequency (hz) t a = 25 c amp = ad8038 full scale loaded to dac zero scale loaded to dac 04461-0-031 0 50 100 150 200 250 300 o u t p u t n o is e ( n v / h z ) midscale loaded to dac f i g u re 31. o u t p ut nois e spe c t r a l d e n s it y
ad5415 rev. 0 | page 15 of 28 gene ral description dac section the ad5415 is a 12-b i t, d u al -cha nn e l , c u r r en t o u t p u t d a c co n s ist i n g o f st anda r d i n v e r t in g r t o 2r ladder co nf igura t io n. a sim p lif i ed dia g r a m o f o n e d a c c h a n n e l f o r th e ad5415 is s h o w n in f i gur e 32. t h e f e e d b a ck r e sis t o r r fb has a va l u e o f 2r . the val u e o f r is typ i cal l y 10 k? (minim u m 8 k? an d max i m u m 12 k ? ) . i f i ou t 1 a n d i ou t 2 a r e k e p t a t t h e s a me p o t e n t ia l , a co n s ta n t c u r r en t f l o w s in each ladder leg, r e ga r d les s o f th e d i g i tal in p u t code . th e r ef o r e , th e i n p u t r e s i s t a n ce p r es en t e d a t v re f is al wa ys co ns t a n t . 2r s1 2r s2 2r s3 2r s12 2r dac data latches and drivers 2r r fb a i out 1a i out 2a v ref a 04461-0-032 rr r f i gure 32. si mpl i fi e d ladde r a ccess is p r o v ide d t o t h e v ref , r fb , i ou t 1, a n d i ou t 2 t e r m inals o f t h e d a c, maki n g t h e de vic e ext r em e l y v e rs a t i l e a n d al lo wi n g i t t o b e conf igur e d in s e v e ral dif f er en t o p er a t in g m o de s, fo r e x am pl e, to prov i d e a u n ip o l ar output , bip o l a r output , or i n s i ng l e - supply m o d e s of op e r a t i o n i n u n ip o l ar m o d e or 4-q u adra n t m u l t i p lic a tion in b i p o la r m o de . unipolar mode u s in g a sin g le op a m p , t h e s e de vices c a n e a sil y be co nf igur e d to prov i d e 2 - q u a d r a n t m u lt iply i n g op e r a t i o n or a u n ip o l ar output v o l t a g e swin g, as s h o w n in f i gur e 33. w h en a n o u t p u t a m p l if ier is co nnec t e d in uni p o l a r m o de , th e o u t p u t v o l t ag e is gi v e n b y v ou t = ? v ref d /2 n wher e: d is t h e f r ac t i o n al r e p r es en t a t i on o f t h e dig i t a l w o r d lo ade d t o th e d a c, in t h e ra n g e o f 0 t o 4095. n is t h e n u m b er o f b i ts. n o t e t h a t t h e ou t p u t v o l t a g e p o la r i ty is o p p o si t e t h e v ref p o l a r i ty fo r dc r e fer e nc e vol t age s . t h ese d a c s a r e d e s i gn e d t o o p e r a t e wi th ei th er n e ga ti v e o r p o si t i v e r e fer e nce v o l t a g es. the v dd p o w e r p i n is used o n l y b y t h e i n t e r n al dig i t a l log i c t o dr i v e t h e d a c s w i t ch es on an d o f f st a t e s . t h ese d a c s a r e also d e s i gn e d t o a cco mm o d a t e a c r e f e r e n c e in p u t sig n als in th e ra n g e o f ?10 v t o +10 v . w i t h a f i x e d 1 0 v re f e re nc e, t h e c i rc u i t i n fi g u re 3 2 g i ve s a uni p ol a r 0 v t o ?10 v o u t p u t vol t a g e s w in g. w h en v in is an ac s i g n a l , t h e c i rc u i t p e r f or ms 2 - q u a d r a n t m u lt ipl i c a t i o n . t a b l e 5 sh o w s th e r e la t i o n s h i p betw een dig i tal co de and exp e c t e d ou t p u t v o l t a g e fo r uni p ola r o p era t io n. table 5. unip o l ar code table digital input analog output (v) 1111 1111 ?v ref (4095/4096) 1000 0000 ?v ref (2048/4096) = ?v ref /2 0000 0001 ?v ref (1/4096) 0000 0000 ?v ref (0/4096) = 0 i out 1a i out 2a r fb a r fb 2r r1 2r ad5415 12-bit dac a r gnd sdin v ref a sclk sync r2 2r r3 2r r2a r2_3a r3a v dd c1 a1 v out = 0v to ?v in a gnd agnd ucontroller agnd r1a notes: 1 dac b omitted for clarity. 2 c1 phase compensation (1pf to 2pf) may be required, if a1 is a high speed amplifier. 04461-0-033 f i g u re 33. u n ipol ar o p er at io n
ad5415 rev. 0 | page 16 of 28 bipolar operation i n s o me a p pl i c a t i o ns , it m i g h t b e ne c e ss ar y to ge ne r a te f u l l 4 - q u a d r a n t m u lt i p ly ing op er a t i o n or a bi p o l a r ou t p ut s w ing . this can be e a si l y acco m p lish e d b y usin g a n o t her ext e r n al a m p l if ier an d t h e o n c h i p 4-q u adra n t r e sis t o r s, as sh o w n in f i gur e 34. w h en i n b i p o lar m o de , t h e o u t p u t v o l t a g e is g i v e n b y v ou t = v ref d /2 n ? 1 ? v ref wher e d is t h e f r ac t i o n al r e p r es en t a t i o n o f t h e dig i t a l w o r d lo aded t o the d a c, in t h e ra n g e o f 0 t o 4095. n is t h e n u m b er o f b i ts. wh e n v in is a n ac sig n al , t h e circ ui t p e r f o r m s 4-q u adra n t mu l t i p l i c a t i o n . t a b l e 6 sh o w s th e r e la t i o n s h i p betw een dig i tal co de and the exp e c t e d ou t p u t v o l t a g e fo r b i p o la r o p era t ion. table 6. bipola r code tabl e digital input analog output (v) 1111 1111 +v ref (2047/2048) 1000 0000 0 0000 0001 ?v ref (2047/2048) 0000 0000 v ref (2048/2048) stability i n t h e i-t o -v conf igura t io n, t h e i ou t o f t h e d a c a n d t h e in v e r t ing no de o f t h e o p a m p m u st b e co nn e c t e d a s clos e as p o s s i b le , and p r o p er pcb l a yo u t t e chni q u es m u s t b e em plo y e d . b e ca us e ev er y co de c h a n ge co r r es p o n d s t o a s t ep f u n c tio n , ga in p e akin g can o c c u r if t h e o p a m p has limi t e d gbp a n d t h er e is exces s i v e p a rasi t i c ca p a c i t a n c e a t t h e i n v e r t in g n o de . this p a rasi t i c c a p a ci t a n c e in t r o d uces a p o le in t o t h e o p en lo o p r e sp o n s e t h a t c a n c a us e r i n g in g o r in st ab i l i t y in t h e clos e d lo o p ap p l i c at i o n s c i r c u i t . an o p tio n al com p en s a tion c a p a ci t o r , c1, ca n b e adde d in pa rall e l w i th r fb for st ab i l it y , as shown i n f i g u re 3 3 and f i gur e 34. t o o smal l a val u e o f c1 can p r o d uce r i n g in g a t t h e o u t p u t , whi l e t o o la rg e a val u e c a n ad vers e l y a f fe c t t h e s e t t l i n g time . c1 sh o u ld be f o und em p i r i cal l y , b u t 1 pf to 2 pf is g e n e rall y ad e q ua t e f o r th e co m p en s a tio n . i out 1a i out 2a r fb a r fb 2r r1 2r ad5415 12-bit dac a r gnd sdin v ref a sclk sync r2 2r r3 2r r2a r2_3a r3a v dd c1 a1 v out =? v in to +v in a1 a gnd ucontroller r1a agnd agnd v in notes: 1 dac b omitted for clarity. 2 c1 phase compensation (1pf to 2pf) may be required, if a1 is a high speed amplifier. 04461-0-034 f i gure 34. bipolar o p er at ion
ad5415 rev. 0 | page 17 of 28 single-supply applications v o lt age swi t chin g mo d e of op erat io n f i gur e 35 s h o w s t h es e d a cs o p era t in g in t h e vol t a g e s w i t chin g mo d e . t h e re f e re nc e vo lt ag e, v in , is a p plie d t o t h e i ou t 1 p i n, i ou t 2 is co nn e c te d t o a g nd , and t h e o u t p u t v o lt a g e is a v a i la b l e at t h e v ref t e r m ina l . i n t h is conf igura t io n, a p o s i t i v e r e fer e n c e volt age re su lt s i n a p o s i t i ve output volt ag e, ma k i ng s i ng l e - su p p ly op e r a t ion p o ss ibl e . t h e ou t p ut f r om t h e d a c is vol t ag e a t a con s t a n t im p e dan c e (t h e d a c ladder r e sis t a n c e ). ther efo r e , a n o p am p is ne ces s a r y t o b u f f er th e o u t p u t v o l t a g e . th e re fe re nc e i n put no l o nge r s e e s a c o nst a n t i n put i m p e d a nc e, but o n e t h a t va r i es wi t h co de . s o , t h e v o l t a g e i n p u t s h o u ld b e dr i v e n f r o m a lo w im p e dan c e s o ur ce. 04461-0-035 v out v dd gnd v in i out 2 i out 1 r fb v dd v ref r 2 r 1 notes 1. similar configuration for dacb 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. f i gure 35. sing le-s up ply v o ltag e s w itching m o de no t e t h a t v in is limi te d t o lo w vol t a g es, b e c a us e t h e s w i t ch es i n t h e d a c ladder n o lo n g er ha ve t h e s a me s o ur ce -dra i n dr i v e v o l t a g e . a s a r e su l t , t h eir on r e sis t an ce dif f ers a n d t h is deg r ade s th e in t e gral lin e a r i t y o f th e d a c . also , v in m ust n o t g o nega t i ve by more t h an 0 . 3 v or an i n te r n a l d i o d e i s tu r n e d on , e x c e e d i n g th e m a xim u m ra ti n g s o f t h e de v i ce . i n th i s t y p e o f a p p l i c a t i o n , t h e f u l l ra n g e o f m u l t i p ly in g c a p a b i li ty o f t h e d a c is los t . posi tive o u tput voltage the o u t p u t v o l t a g e p o l a r i ty is op p o si t e t o t h e v ref po l a ri t y f o r dc r e fer e n c e v o lt a g es. t o achie v e a p o si t i ve v o l t a g e o u t p u t , an a p plie d n e g a t i v e r e fer e n c e t o t h e in p u t o f t h e d a c is p r efer r e d o v er t h e o u t p u t in v e rsion t h r o ug h a n i n v e r t in g a m plif ier b e ca us e o f t h e resis t o r s t o lera nce er r o rs. t o g e n e ra t e a nega t i ve re f e re nc e, t h e re f e re nc e c a n b e l e vel - sh i f te d by an op a m p su ch th a t t h e v ou t a n d gnd p i n s o f t h e r e fer e nce b e c o m e t h e vir t ual gr o u n d and ?2. 5 v , r e s p ec ti v e l y , as sh o w n in f i gur e 36. v dd r fb i out 1 i out 2 c1 v out = 0 to +2.5v gnd v dd = 5v v ref notes: 1 additional pins omitted for clarity. 2 c1 phase compensation (1pf to 2pf) may be required, if a1 is a high speed amplifier. 1/2 ad8552 12-bit dac 1/2 ad8552 adr03 v out v in gnd ?5v +5v ? 2.5v 04461-0-036 f i g u r e 3 6 . p o s i ti v e v o l t a g e ou t p u t w i th mi ni m u m o f c o m p o n e n t s adding g a in i n a p plic a t io n s wher e t h e o u t p u t v o l t a g e is r e quir e d t o b e gr ea t e r th a n v in , ga i n ca n be a d d e d wi th a n a ddi ti o n al ext e rn al a m p l if ier , o r i t c a n also b e ac hie v ed in a single sta g e . i t is im p o r t an t t o t a k e i n t o con s ider a t io n t h e ef fe c t o f t e m p er a t ur e co ef f i cien ts o f t h e t h in f i lm r e si s t o r s o f t h e d a c. sim p ly placi n g a r e sisto r in s e r i es wi t h t h e r fb r e sis t o r ca us es misma t ch es in t h e t e m p era t ur e co ef f i cien ts, r e s u l t in g i n la rg er ga i n t e m p er a t ur e c o e f f i c i e n t e r ror s . i n ste a d, t h e c i rc u i t i n f i g u re 3 7 i s a re c o m - me nd e d me t h o d of i n c r e a s i ng t h e g a i n of t h e c i rc u i t . r 1 , r 2 , a n d r 3 s h o u l d al l ha v e simi l a r t e m p era t ur e co ef f i cie n ts, b u t t h e y n e e d n o t ma t c h t h e tem p era t ur e co ef f i cien ts o f t h e d a c. this a p p r o a ch is r e c o mmende d in c i r c ui ts w h er e gain s o f g r e a t e r t h an 1 are re qu i r e d . v dd r fb i out 1 i out 2 c1 gnd v dd v ref notes: 1 additional pins omitted for clarity. 2 c1 phase compensation (1pf to 2pf) may be required, if a1 is a high speed amplifier. 12-bit dac v in r2 r3 r2 v out r1 = r2r3 r2 + r3 gain = r2 + r3 r2 04461-0-037 f i gure 3 7 . incr ea si ng the g a i n o f the current o u tput d a c div i der or programm able gain e l ement c u r r en t-st e e r i ng d a cs a r e v e r y f l exi b le a n d le nd t h e m s e lv es to ma n y dif f er en t a p plic a t ion s . i f t h is typ e o f d a c is co nne c t e d as th e f e e d ba ck e l em en t o f a n o p a m p a n d r fb is us e d as t h e in p u t re s i stor , a s show n i n fi g u re 3 8 , t h e n t h e output vo lt age i s i n v e r s e l y p r o p o r ti o n al t o th e digi tal in p u t f r a c tio n , d . f o r d eq ual t o 1 ? 2 n , t h e o u t p u t v o l t a g e is v ou t = ? v in / d = ? v in /(1 ?2 ? n )
ad5415 rev. 0 | page 18 of 28 v in note: 1 additional pins omitted for clarity. v ref v dd v dd r fb i out 1 i out 2 gnd v out 04461-0-038 f i gure 38. cur r ent- stee ring d a c used as a d i v i d e r or p r og r a m m ab le g a in e l em ent as d is r e d u ce d , t h e o u t p u t v o l t a g e i n cr e a s e s. f o r smal l val u es o f th e d i g i tal f r acti o n , d , i t is im p o r t a n t t o en s u r e tha t t h e a m plif ier do es n o t s a t u ra te an d a l s o t h a t t h e r e q u ir e d acc u rac y is m e t. f o r exa m ple , a n 8 - b i t d a c dr i v en wi t h t h e b i na r y co de 0x10 (0001 000 0), tha t is, 16 decimal , in t h e circ ui t o f f i gur e 37 shou l d c a u s e t h e output vo lt age to b e 1 6 t i me s v in . h o w e v e r , i f t h e d a c has a l i n e a r i t y sp e c if ic a t io n o f 0.5 lsb , t h en d can, in fac t , ha v e a w e ig h t an y w h e r e in th e ra n g e 15.5/2 56 t o 16.5/256, s o t h a t t h e p o s s ib le o u t p u t v o l t ag e is in t h e ra n g e 15.5 v in to 16.5 v in , a n er r o r o f 3% e v en t h o u g h t h e d a c i t s e lf has a max i m u m er r o r o f 0.2%. d a c le aka g e c u r r en t is als o a p o t e n t ial er r o r s o ur ce in di vi der cir c ui ts. th e le a k a g e c u r r en t m u s t b e co u n t e rb alan ce d b y a n opp o s i te c u r r e n t suppl i e d f r om t h e op a m p t h ro u g h t h e d a c . b e ca us e o n ly a f r ac t i o n d o f t h e c u r r en t in t o t h e v ref te r m i n a l is r o u t ed t o t h e i ou t 1 t e r m inal, t h e o u t p u t v o l t a g e has t o cha n ge as fol l o w s: o u tp u t e r r o r v o l t a ge d u e t o d a c le a k a ge = ( l e ak ag e r )/ d wher e r is t h e d a c r e sis t an ce a t t h e v ref te r m i n a l . f o r a d a c leaka g e c u r r en t o f 10 na, r = 10 k?, a n d a ga in (tha t is, 1/d) o f 16, th e er r o r v o l t a g e is 1.6 mv . reference selection w h en s e le c t in g a r e fer e n c e fo r us e wi t h t h e ad 54xx s e r i es o f c u r r e n t ou t p u t d a c s , p a y a t te n t i o n to t h e re fe re nc e s out p ut v o l t a g e t e m p era t ur e co ef f i cien t s p e c if ic a t ion. this p a ra m e t e r a f fe c t s n o t only t h e f u l l -s cale er r o r , b u t ca n als o a f fe c t t h e lin e a r i t y (inl and d n l) p e r f o r ma nce . th e r e fe r e n c e tem p era - t u r e co ef f i cien t s h o u ld b e co n s i s t e n t wi t h t h e s y s t em acc u rac y sp e c if ic a t ion s . f o r exa m ple , a n 8-b i t syst e m r e quir e d t o h o ld i t s o v eral l s p e c if ica t io n t o wi t h in 1 ls b o v er t h e t e m p er a t ur e ra n g e 0c t o 50c dic t a t es tha t t h e maxim u m sy ste m dr if t wi th t e m p era t ur e sho u ld b e les s t h an 78 p p m/c. a 12-b i t sys t em wi t h t h e s a me tem p er a t ur e rang e t o o v eral l s p e c if ica t ion wi t h i n 2 ls b r e q u ir es a maxim u m dr if t o f 10 p p m /c. b y c h o o sin g a p r e c isio n r e fer e n c e wi t h a lo w o u t p u t t e m p er a t ur e co ef f i cien t, t h is er r o r s o ur ce can b e minimi ze d . t a b l e 7 s u g g es ts s o m e o f t h e r e fer e n c e s a v a i lab l e f r o m a n alog d e v i ces t h a t a r e s u i t ab le fo r us e wi t h t h is ra n g e o f c u r r en t o u t p u t d a c s . amplifier selection the p r ima r y r e q u ir em e n t fo r t h e c u r r en t- s t e e r i n g m o de is a n a m plif ier wi t h lo w in p u t b i as c u r r en ts a n d lo w in p u t o f fs et volt age. t h e i n put of f s e t volt age of an op am p i s m u lt i p l i e d b y th e va r i a b le ga in (d ue t o t h e co de-dep en den t o u t p u t r e sis t an ce o f t h e d a c) o f t h e cir c ui t. a cha n g e i n t h is n o i s e ga in b e tw e e n tw o ad j a cen t di g i t a l f r ac t i o n s pr o d uces a step cha n ge i n t h e o u t p u t v o l t a g e d u e t o t h e am plif ier s in p u t o f fs et v o l t a g e . thi s o u t p u t v o l t a g e cha n g e is s u p er im p o s e d u p on t h e desir e d chang e in o u t p u t b e tw e e n t h e t w o co de s a n d g i ves r i s e to a dif f er en t i a l lin e a r i t y er r o r , which, if l a rg e en o u g h , co u l d ca us e t h e d a c t o b e n o n m on oto n ic. t h e in p u t b i as c u r r en t o f a n o p a m p also g e nera t e s a n o f fset a t t h e v o l t a g e o u t p u t as a r e s u l t o f t h e b i as c u r r en t f l o w in g in t h e f eed ba ck r e s i s t o r , r fb . m o s t o p a m ps ha ve in p u t b i as c u r r en ts lo w en o u g h t o pr e v en t an y sig n i f ica n t er r o rs in 12-b i t ap p l i c at i o n s . c o mm on- m o d e r e j e c t io n o f t h e o p a m p is i m p o r t a n t in v o lt a g e swi t c h in g cir c ui ts, be ca us e i t p r o d uces a c o de-dep e n de n t er r o r a t t h e v o l t a g e o u t p u t o f th e cir c ui t. m o s t o p a m ps ha v e adeq ua te c o m mon - m o d e re j e c t i o n f o r u s e a t 1 2 - bit re s o lut i on . p r o v ide d t h a t t h e d a c s w i t ch e s a r e dr i v en f r o m t r ue wideb a nd lo w im p e dan c e s o ur ces (v in and a g n d ), they set t le q u ickl y . c o n s eq uen t l y , t h e s l ew r a t e and set t ling tim e o f a v o l t a g e swi t c h in g d a c cir c ui t is det e r m in e d la rg e l y b y t h e o u t p u t o p a m p . t o ob t a in mini m u m s e t t li n g t i m e i n t h is c o nf igura t io n, i t is im p o r t an t t o mini mi ze c a p a c i t a n c e a t t h e v re f no de ( v ol t a ge o u t p ut no de i n t h is a p plic a t ion) o f t h e d a c. this is do ne b y usin g lo w in p u t s , ca p a ci t a n c e b u f f er a m plif iers, a n d ca r e f u l b o a r d desig n . m o s t sin g le-s u p p l y cir c ui ts in cl ude g r o u n d as p a r t o f t h e a n alog sig n a l ra n g e , w h ich in t u r n r e q u ir es a n am plif ie r t h a t can han d l e ra il-t o-ra il signals. a la r g e ra n g e o f sin g le-s u p pl y a m p l if ier s is av a i l a b l e f r o m a n a l o g d e v i c e s .
ad5415 rev. 0 | page 19 of 28 table 7. adi precision references for use with ad54xx dacs reference output voltage (v) initial tolerance (%) tem p. drift (ppm/c) 0.1 hz to 10 hz noise package adr01 10 0.1 3 20 v p-p sc70, tsot, soic adr02 5 0.1 3 10 v p-p sc70, tsot, soic adr03 2.5 0.2 3 10 v p-p sc70, tsot, soic adr425 5 0.04 3 3.4 v p-p msop, soic table 8. precision adi op am ps for use with ad54xx dacs part no. max supply voltage (v) v os (max) v i b (max) na gbp mhz slew rate (v/s) op97 20 25 0.1 0.9 0.2 op1177 18 60 2 1.3 0.7 ad8551 6 5 0.05 1.5 0.4 table 9. high speed adi op am ps for use with ad54xx dacs part no. max supply voltage (v) v os (max) v i b (max) na bw @ a cl mhz slew rate (v/s) ad8065 12 1500 0.01 145 180 ad8021 12 1000 1000 200 100 ad8038 5 3000 0.75 350 425
ad5415 rev. 0 | page 20 of 28 serial interface the ad5415 has a n easy-t o-us e 3-wir e in t e r f ace , whic h is co m p a t i b le wi th s p i, qs p i , mi cr o w ire, an d ds p in t e r f ace s t a n d a r d s . da ta i s w r i t t e n t o th e d e v i ce in 16-b i t w o r d s . e a c h 16-b i t w o r d consis ts o f f o ur co n t r o l b i ts and 12 da ta b i ts, as s h own in f i gur e 39. low power serial interf ace t o mi nimize t h e p o w e r co n s u m p t ion o f t h e de v i ce , t h e i n t e r f ace p o w e r s u p f u l l y o n l y when t h e devi c e i s b e i n g w r i t te n to , t h a t i s , on t h e f a l l i n g e d ge of sy n c . the sc lk an d d i n i n p u t b u f f ers are p o we re d d o w n on t h e r i s i n g e d ge of sy n c . dac control bits c3 to c0 c o n t ro l bit s c 3 to c 0 a l l o w c o n t ro l of v a r i ou s f u nc t i ons of t h e d a c, as sh o w n in t a b l e 11. def a ul t set t in gs o f th e d a c a t p o w e r - o n a r e as f o l l o w s. da ta is c l o c k e d in t o the s h if t r e gis t er o n fa l l in g clo c k e d ges; da isy-chain m o de is ena b le d . th e de vice p o w e r s o n wi th zer o -sc a le lo ad t o th e d a c r e gis t er an d i ou t lin e s. the d a c co n t r o l b i ts al lo w the us er t o ad j u s t cer t a i n fe a t ur es a t p o w e r - o n . f o r exa m ple , da isy-chaini n g can b e disa b l e d w h en n o t in use , ac ti ve cl o c k e d g e c a n b e change d to ri s i n g ed g e , a n d d a c o u t p u t ca n b e c l ea r e d t o e i th e r z e r o scale o r m i dscale . the user ca n also ini t ia t e a r e ad bac k o f th e d a c r e g i s t er co n t en t s fo r v e r i f i ca t i o n p u r p os es. contr o l register (control bits = 1101) w h i l e main t a inin g s o f t wa r e com p a t i b i l i t y w i t h t h e sin g le - c h a n n e l c u r r en t o u t p u t d a cs ( a d5426/ad54 33/ad5443), this d a c also f e a t ur es so m e a d di ti o n al i n terfa c e fun c ti o n ali t y . s i m p l y s e t t h e c o n t r o l b i ts t o 11 01 t o en t e r con t r o l r e g i s t er m o de . f i gur e 40 s h o w s t h e con t en ts o f t h e co n t r o l r e g i s t er , t h e f u nc t i ons of w h i c h are d e s c r i b e d i n t h e f o l l ow i n g s e c t i o ns . sdo cont rol (sdo1 an d s d o2) the s d o b i ts e n a b le t h e us er to co n t r o l t h e sd o o u t p u t dr i v er s t r e n g t h , dis a b l e t h e s d o o u t p u t , o r co nf igur e i t as an o p e n - dra i n dr i v er . the s t r e n g t h o f t h e s d o dr i v er a f fe c t s t h e t i ming of t 12 a n d , w h en s t r o n g er , al lo ws a fas t er clo c k c y cle t o b e us e d . table 10. s d o control bits sd o2 sd o1 fu nction 0 0 full sdo driver 0 1 sdo configured as open drai n 1 0 weak sdo drive r 1 1 disable sdo output daisy-ch ain c o ntrol (dsy) ds y enab les o r dis a b l es da isy - cha i n m o de. a 1 ena b les d a isy - cha i n m o de; a 0 dis a b l es it. w h e n dis a b l e d , a r e a d b a ck r e q u est is accep t e d , s d o is a u t o ma t i cal l y ena b le d , t h e d a c r e g i s t er co n t en ts o f t h e r e levan t d a c a r e c l o c k e d o u t o n s d o , and , w h e n c o m p l e te, sd o i s d i s a bl e d ag ai n . hardware clr bit (hclr) t h e d e fa ul t set t in g f o r th e h a r d w a r e clr pi n i s to c l e a r t h e re g i ste r s and d a c ou t p ut to ze ro c o de. a 1 in t h e h c l r bi t c l ea r s th e d a c o u t p u t s t o m i d s cale ; a 0 c l ea r s th em t o zer o s c a l e. active clock e d ge (sclk) the def a u l t ac t i v e c l o c k e d ge is t h e fal l in g e d ge . w r i t e a 1 t o t h is b i t t o c l o c k da ta in o n t h e r i sin g edg e ; wr i t e a 0 to c l o c k i t o n t h e fal l in g e d ge . data bits control bits c3 c2 c1 c0 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db0 (lsb) db15 (msb) 04461-0-039 f i g u re 39. a d 5 4 1 5 12-b i t inpu t shi f t regi st er c o nt ents control bits 11 0 1 sdo1 sdo2 dsy hclr sclk xx xxx x x db0 (lsb) db15 (msb) 04461-0-040 f i gure 40. cont r o l r e gister l oad ing s e quence
ad5415 rev. 0 | page 21 of 28 table 11. dac control bits c3 c2 c1 c0 dac function 0 0 0 0 a and b no operation (power-on default) 0 0 0 1 a load and update 0 0 1 0 a initiate readback 0 0 1 1 a load input register 0 1 0 0 b load and update 0 1 0 1 b initiate readback 0 1 1 0 b load input register 0 1 1 1 a and b update dac outputs 1 0 0 0 a and b load input registers 1 0 0 1 C daisy-chain disable 1 0 1 0 C clock data to shift register on rising edge 1 0 1 1 C clear dac output to zero 1 1 0 0 C clear dac output to midscale 1 1 0 1 C control word 1 1 1 0 C reserved 1 1 1 1 C no operation sync function sync is an edge-triggered input that acts as a frame synchroni- zation signal and chip enable. data can be transferred into the device only while sync is low. to start the serial data transfer, sync should be taken low, observing the minimum sync falling to sclk falling edge setup time, t 4 . daisy-chain mode daisy-chain mode is the default mode at power-on. to disable the daisy-chain function, write 1001 to the control word. in daisy-chain mode, the internal gating on sclk is disabled. the sclk is continuously applied to the input shift register when sync is low. if more than 16 clock pulses are applied, the data ripples out of the shift register and appears on the sdo line. this data is clocked out on the rising edge of sclk and is valid for the next device on the falling edge (default). by connecting this line to the din input on the next device in the chain, a multidevice interface is constructed. sixteen clock pulses are required for each device in the system. therefore, the total number of clock cycles must equal 16 n , where n is the total number of devices in the chain. (see the timing diagram in figure 4.) when the serial transfer to all devices is complete, sync should be taken high. this prevents any further data from being clocked into the input shift register. a burst clock containing the exact number of clock cycles can be used and sync taken high some time later. after the rising edge of sync , data is automati- cally transferred from each devices input shift register to the addressed dac. when control bits are 0000, the device is in no-operation mode. this might be useful in daisy-chain applications, where the user does not want to change the settings of a particular dac in the chain. simply write 0000 to the control bits for that dac, and the following data bits are ignored. standalone mode after power-on, writing 1001 to the control word disables daisy- chain mode. the first falling edge of sync resets a counter that counts the number of serial clocks to ensure that the correct number of bits is shifted in and out of the serial shift registers. a sync edge during the 16-bit write cycle causes the device to abort the current write cycle. after the falling edge of the 16th sclk pulse, data is automati- cally transferred from the input shift register to the dac. in order for another serial transfer to take place, the counter must be reset by the falling edge of sync . ldac function the ldac function allows asynchronous or synchronous updates to the dac output. the dac is asynchronously updated when this signal goes low. alternatively, if this line is held permanently low, an automatic or synchronous update mode is selected, whereby the dac is updated on the 16th clock falling edge when the device is in standalone mode or on the rising edge of sync when in daisy-chain mode. software ldac function load and update mode also functions as a software update function, irrespective of the voltage level on the ldac pin.
ad5415 rev. 0 | page 22 of 28 microprocessor interfacing m i cr o p r o ces s o r in t e r f acing t o th e ad5415 d a c is thr o ug h a s e r i al b us t h a t us es s t anda r d p r o t o c ol co m p a t ib le wi t h micr o - co n t r o l l ers a n d ds p p r o c es s o rs. the co mm unic a t io n s cha n n e l i s a 3- wir e i n ter f a c e co n s ist i n g o f a clo c k sig n a l , a d a t a sig n a l , a n d a sy n c hr o n iza t io n sig n al . th e ad5415 r e q u ir es a 16-b i t w o rd , w i th th e d e fa u l t b e i n g d a ta v a l i d o n th e f a ll i n g e d g e o f s c l k , b u t this is c h a n g e a b le usin g the co n t r o l b i ts in t h e da ta-w o r d . adsp-21xx to ad5415 interface t h e ads p -21xx fa m i l y o f ds p s is easil y in t e r f ac ed t o t h e ad5415 d a c wi t h o u t t h e n e e d f o r extra g l ue log i c. f i gur e 40 is a n exa m ple o f a n s p i in t e r f ace b e tw e e n t h e d a c a n d t h e ads p -2191m. s c k o f th e ds p dr i v es th e s e r i al da ta line , d i n. s y n c is dr i v en f r o m o n e o f the p o r t lin e s, in this case s p i x s e l. sclk sck sync spixsel sdin mosi adsp-2191* *additional pins omitted for clarity ad5415* 04461- 0- 041 f i g u re 41. a d s p -2 1 91 spi to a d 5 4 1 5 i n ter f ac e a se ri al in t e rf a c e bet w een th e d a c a n d ds p s p o r t i s s h o w n in f i gur e 42. i n t h is in t e r f ace ex a m ple , s p o r t0 is us e d t o t r a n sfer da t a t o t h e d a c sh if t r e g i st er . t r a n smi s sio n is ini t ia t e d b y wr i t in g a w o r d t o t h e tx r e g i s t er a f t e r t h e spo r t has b e en ena b led . i n a wr i t e s e q u en ce , da ta is c l o c k e d o u t o n eac h r i sin g e d ge of t h e ds p s s e r i a l cl o c k and cl o c ke d i n to t h e d a c i n p u t s h if t r e g i st er o n t h e fal l i n g e d g e o f i t s sclk. the u p da t e o f t h e d a c o u t p u t t a k e s place on t h e r i sin g e d g e o f t h e s y nc sig n al. sclk sclk sync tfs sdin dt adsp-2101/ adsp-2103/ adsp-2191* *additional pins omitted for clarity 04461- 0- 042 ad5415* f i gur e 4 2 . adsp -210 1/ adsp -21 03/ adsp -2 19 1 sp or t to ad5 4 1 5 int e r f a c e c o mm uni c a t ion b e twe e n tw o de vices a t a g i ve n clo c k sp e e d is p o ssi b le w h en t h e fol l o w in g sp e c if ica t ion s a r e co m p a t i b le: f r a m e sy n c de la y a n d f r a m e sy n c set u p-a n d-h o ld , da t a d e la y a n d d a t a s e t u p - and- h o ld , and scl k wi d t h. the d a c in ter f ace exp e c t s a t 4 ( s y n c fal l in g edg e t o sclk fal l in g edg e set u p tim e ) o f 13 n s mini m u m. s e e t h e ads p -21xx u ser m a n u a l fo r info r m a t io n on clo c k an d f r am e syn c f r e q ue n c ie s fo r t h e sp or t re g i s t e r . t a b l e 12 sh o w s t h e s e t u p fo r t h e s p o r t co n t rol r e g i s t er . table 12. spo r t co ntrol r e gister setup name setting description t f s w 1 alternate f r a m i n g invt fs 1 active low fram e signal dtype 00 right-justify dat a isclk 1 internal seri al cl ock tfsr 1 frame every wo rd itfs 1 internal framing signal s l e n 1 1 1 1 16-bit d a t a - w o r d 80c51/80 l51 to ad5415 interface a s e r i al i n t e r f ac e b e tw e e n t h e d a c a n d t h e 80c 51 is s h o w n i n f i gur e 43. t x d o f th e 80c51 dr i v es sclk o f t h e d a c s e r i al in t e r f ace , whi l e r x d dr i v es t h e s e r i al da t a li n e , d i n. p3.3 is a b i t-p r og ra mmab l e p i n o n t h e s e r i al p o r t an d is us e d t o dr i v e s y nc . w h e n d a t a i s to b e t r ans m i tte d to t h e s w itch, p 3 . 3 i s tak e n lo w . th e 80c51/80l51 tr a n smi t s da t a o n l y in 8-b i t b y t e s; t h er efo r e , o n ly eig h t fal l i n g clo c k e d g e s o c c u r i n t h e t r a n smi t c y c l e . t o lo ad da ta co r r ec tl y t o th e d a c, p3.3 is lef t lo w a f t e r th e f i rs t eig h t b i ts ar e t r a n smi t t e d , a n d a s e con d wr i t e c y cle is i n i t i a te d to t r ans m i t t h e s e c o nd b y te of d a t a . d a t a on r x d i s cl o c ke d out of t h e m i c r o c on t r o l l e r on t h e r i s i ng e d ge of t x d a n d is valid o n t h e fal l in g edge . a s a r e s u l t , n o g l ue logic is r e q u i r ed be tw een th e d a c a n d m i cr oco n tr o l le r i n t e rfa c e . p 3 .3 is tak e n hig h f o l l o w in g t h e com p letio n o f this c y c l e . th e 80c51 p r o v ides t h e lsb o f i t s s b uf r e g i s t er as t h e f i rst b i t i n t h e da t a s t r e a m . th e d a c in p u t r e g i s t er r e q u ir es i t s da t a wi t h t h e ms b as t h e f i rs t b i t r e cei v e d . th e t r a n smi t r o u t i n e sho u ld t a k e t h is in t o acco u n t. sclk tx d 8051* sync p1.1 sd i n rx d *additional pins omitted for clarity 04461- 0- 043 ad5415* f i g u re 43. 8 0 c5 1/ 8 0 l5 1 t o a d 54 15 int e r f ace mc68hc11 interface to a d 5415 interface f i gur e 44 is a n e x a m ple o f a s e r i al in t e r f ace b e t w e e n t h e d a c a n d t h e m c 68 h c 11 micr o c on tr ol ler . th e s e r i al p e r i p h eral in t e r f ace (s p i ) o n the m c 68h c11 is co nf igur ed f o r mas t er m o de (ms t r) = 1, clo c k p o la r i ty b i t (cpo l) = 0, a n d t h e c l o c k phas e b i t (c ph a) = 1. th e spi is co nf igur e d b y wr i t ing t o t h e s p i co n t r o l r e g i s t er (s pcr); s e e th e 68 h c 11 u s er m a n u a l . s c k o f t h e 68h c11 dr i v es t h e s c l k o f t h e d a c i n t e r f ace , t h e m o s i o u t p u t dr i v es t h e s e r i al da ta lin e (d in) o f th e ad5516. the s y n c sig n a l is der i ve d f r o m a p o r t li n e ( p c7) . w h e n da t a is bein g tra n smi t t e d t o t h e ad5 516, th e s y n c l i ne is ta k e n lo w ( p c 7 ) . d a t a a p p e ar i n g on t h e m o si output i s v a l i d on t h e fal l in g edg e o f s c k. s e r i al da t a f r o m th e 68 h c 1 1 is tra n sm i t t e d in 8- b i t b y t e s wi t h o n ly eig h t fa l l in g clo c k e d ges o c c u r r i n g in
ad5415 rev. 0 | page 23 of 28 th e tra n sm i t c y cle . da ta i s tra n sm i t t e d m s b f i r s t . t o loa d d a ta t o th e d a c , p c 7 is le ft lo w a f t e r th e f i r s t ei gh t b i ts a r e tra n s f e r r e d , an d a s e c o nd s e r i a l w r it e op e r a t i o n i s p e r f or me d to t h e d a c . p c 7 i s tak e n h i gh a t t h e en d o f th i s p r oced u r e . sclk sck ad5415* sync pc7 sdin mosi mc68hc11* *additional pins omitted for clarity 04461- 0 - 0 44 f i g u re 44. 6 8 hc 1 1 / 68l 11 to a d 5 4 1 5 i n ter f ac e i f th e u s e r w a n ts t o v e ri f y th e da ta p r e v i o u s l y wri t t e n t o th e in p u t shif t r e g i st er , t h e s d o li ne can b e co nn e c t e d t o mis o o f th e m c 68 h c 11 , a n d , wi th s y nc lo w , th e s h if t r e g i s t er c l o c ks d a t a out on t h e r i s i ng e d ge s of s c l k . microwire to ad5415 interface f i gur e 45 s h o w s a n i n t e r f ace b e t w e e n t h e d a c a n d an y mi cro w i r e-co m p a t i b le de vice . s e r i al da ta is s h if t e d o u t on th e fal l in g edge o f th e ser i al c l o c k, s k , an d is c l o c k e d in t o t h e d a c in p u t shif t r e gis t er o n t h e r i sin g edg e o f s k , which co r r es p o n d s t o t h e fal l i n g e d ge o f t h e d a c s s c lk. sclk sk microwire* sync cs sdin so ad5415* *additional pins omitted for clarity 04461- 0- 045 f i g u re 45. m i cr o w ir e to a d 5 4 15 i n te r f ac e pic16c6x/7x t o ad5415 interface the p i c16c6x/7x syn c hr on o u s s e r i al p o r t (ss p ) is co nf igur ed as a n spi ma ste r wi t h t h e clo c k p o la r i ty b i t (c k p ) = 0. this is do ne b y wr i t in g t o t h e sy n c hr o n o us s e r i al p o r t co n t r o l r e g i s t er (ss p c o n); s e e t h e p i c 16/ 17 m i cr oco n tr o l l e r u s er m a n u a l . i n this exa m p l e , i/o p o r t ra1 is used t o p r o v ide a s y n c signal a n d enab le the s e r i al p o r t o f th e d a c. t h is mic r o c o n tr o l ler t r a n sfers o n l y eig h t b i ts o f da t a d u r i n g e a c h s e r i al t r a n sfer o p era t ion; t h er e f o r e , tw o co n s e c u t i v e wr i t e op era t io n s a r e re qu i r e d . f i g u re 4 6 show s t h e c o n n e c t i on d i ag r a m . sclk sck/rc3 pic16c6x/7x* sync ra1 sdin sdi/rc4 ad5415* *additional pins omitted for clarity 04461- 0- 046 f i g u re 46. pic 16c 6 x /7x t o a d 54 15 int e r f ace
ad5415 rev. 0 | page 24 of 28 pcb layout and power supply decoupling in any circuit where accuracy is important, careful considera- tion of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5415 is mounted should be designed so that the analog and digital sections are separated, and confined to certain areas of the board. if the dac is in a system where multiple devices require an agnd-to-dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. the dac should have ample supply bypassing of 10 f in parallel with 0.1 f on the supply located as close to the package as possible, ideally right up against the device. the 0.1 f capacitor should have low effective series resistance (esr) and effective series inductance (esi), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. low esr 1 f to 10 f tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough on the board. a microstrip technique is by far the best, but not always possible with a double-sided board. in this technique, the component side of the board is dedicated to the ground plane while signal traces are placed on the soldered side. it is good practice to employ compact, minimum lead length pcb layout design. leads to the input should be as short as possible to minimize ir drops and stray inductance. the pcb metal traces between v ref and r fb should also be matched to minimize gain error. to maximize on high fre- quency performance, the i-to-v amplifier should be located as close to the device as possible. evaluation board for the dac the evaluation board consists of an ad5415 dac and a current-to-voltage amplifier, ad8065. included on the evaluation board is a 10 v reference, adr01. an external reference can also be applied via an smb input. the evaluation kit consists of a cd-rom with self-installing pc software to control the dac. the software allows the user to write a code to the device. power supplies for the evaluation board the board requires 12 v and +5 v supplies. the +12 v v dd and v ss are used to power the output amplifier, while the +5 v is used to power the dac (v dd1 ) and transceivers (v cc ). both supplies are decoupled to their respective ground plane with 10 f tantalum and 0.1 f ceramic capacitors.
ad5415 rev. 0 | page 25 of 28 v re f b u1 ad5415 p1 ?19 p1 ?20 p1 ?21 p1 ?22 p1 ?23 p1 ?24 p1 ?25 p1 ?26 p1 ?27 p1 ?28 p1 ?29 p1 ?30 v dd p2? 3 p2? 2 p2? 1 p2? 4 agnd v ss v dd 1 v dd c1 1 0.1 f c1 2 10 f c1 3 0.1 f c1 4 10 f c1 5 0.1 f c1 6 10 f + + + v dd v ss u3 c8 1.8pf c7 10 f c8 0.1 f 7 4 3 2 6 v? v+ + c9 10 f c1 0 0.1 f + tp1 j1 v out a v dd v ss u4 c1 7 1.8pf c1 8 10 f c1 9 0.1 f 7 4 3 2 6 v? v+ + c2 0 10 f c2 1 0.1 f + tp2 j2 v out b v dd 1 c2 10 f c1 0.1 f + v dd v ss u5 c2 2 10 f c2 3 0.1 f 7 4 3 2 6 v? v+ + c2 4 10 f c2 5 0.1 f + a d 8065a r j3 j4 j5 j6 j7 lk1 ab r3 b r 2?3b i out 2b i out 1b r fb b r2 b r1 b v re f a r3 a r 2?3a r2 a i out 2a i out 1a r1 a r fb a gnd clr sd o ldac syn c sd in sc lk 3 4 1 2 5 6 7 8 21 20 22 24 23 19 18 17 16 9 11 12 14 10 13 15 clr sd o ldac syn c sd in sc lk r1 10k ? v dd 1 r2 10k ? v dd 1 r3 10k ? v dd 1 clr sd o ldac syn c sd in sc lk p1? 2 p1? 3 p1? 4 p1? 5 p1? 1 3 p1? 6 v dd +v in v out trim gnd c3 10 f c4 0.1 f u2 adr01ar 4 5 4 3 1 c4 0.1 f lk2 lk3 v re f j8 v in j10 a b v re f a 04461-0-047 f i g u re 47. s c he mat i c of t h e a d 5 4 1 5 ev al uat i on bo ar d
ad5415 rev. 0 | page 26 of 28 04461-0-048 f i g u re 48. co mpon ent - side a r t w ork 04461-0-049 f i gure 49. si lks c ree n c om pon e nt-si d e vie w ( t op)
ad5415 rev. 0 | page 27 of 28 04461-0-050 f i gure 50. s o ld er -si d e a r t w o r k table 13. over view o f ad54 x x de vices part no. resolution no. dacs inl(lsb) interface package features ad5424 8 1 0.25 paralle l ru-16, cp-20 10 mhz bw, 17 ns cs pulse width ad5426 8 1 0.25 serial rm-10 10 mhz bw, 50 mhz serial ad5428 8 2 0.25 paralle l ru-20 10 mhz bw, 17 ns cs pulse width ad5429 8 2 0.25 serial ru-10 10 mhz bw, 50 mhz serial ad5450 8 1 0.25 serial rj-8 10 mhz bw, 50 mhz serial ad5432 10 1 0.5 serial rm-10 10 mhz bw, 50 mhz serial ad5433 10 1 0.5 paralle l ru-20, cp-20 10 mhz bw, 17 ns cs pulse width ad5439 10 2 0.5 serial ru-16 10 mhz bw, 50 mhz serial ad5440 10 2 0.5 paralle l ru-24 10 mhz bw, 17 ns cs pulse width ad5451 10 1 0.25 serial rj-8 10 mhz bw, 50 mhz serial ad5443 12 1 1 serial rm-10 10 mhz bw, 50 mhz serial ad5444 12 1 0.5 serial rm-8 10 mhz bw, 50 mhz serial ad5415 12 2 1 serial ru-24 10 mhz bw, 58 mhz serial a d 5 4 4 5 1 2 2 1 paralle l ru-20, c p - 2 0 10 mhz bw, 17 ns cs pulse width ad5447 12 2 1 paralle l ru-24 10 mhz bw, 17 ns cs pulse width ad5449 12 2 1 serial ru-16 10 mhz bw, 50 mhz serial ad5452 12 1 0.5 serial rj-8, rm-8 10 mhz bw, 50 mhz serial ad5446 14 1 1 serial rm-8 10 mhz bw, 50 mhz serial ad5453 14 1 2 serial uj-8, rm-8 10 mhz bw, 50 mhz serial ad5553 14 1 1 serial rm-8 4 mhz bw, 50 mhz serial clock a d 5 5 5 6 1 4 1 1 paralle l r u - 2 8 4 mhz bw, 20 ns wr pulse width ad5555 14 2 1 serial rm-8 4 mhz bw, 50 mhz serial clock a d 5 5 5 7 1 4 2 1 paralle l r u - 3 8 4 mhz bw, 20 ns wr pulse width ad5543 16 1 2 serial rm-8 4 mhz bw, 50 mhz serial clock a d 5 5 4 6 1 6 1 2 paralle l r u - 2 8 4 mhz bw, 20 ns wr pulse width ad5545 16 2 2 serial ru-16 4 mhz bw, 50 mhz serial clock a d 5 5 4 7 1 6 2 2 paralle l r u - 3 8 4 mhz bw, 20 ns wr pulse width
ad5415 rev. 0 | page 28 of 28 outline dimensions 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153ad f i gure 51. 2 4 -l ead thin shr i nk s m a l l o u tline p a ckage [ t ssop ] (ru - 24) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model resolution inl (lsbs) temperature r a nge package descri ption package option ad5415yru 12 1 ?40c to +125c tssop ru-24 ad5415yru-re el 12 1 ?40c to +125c tssop ru-24 ad5415yru-re el7 12 1 ?40c to +125c tssop ru-24 eval-ad5415 e b e v a l u a t i o n k i t ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . d04461C0C 7/04(0)

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